TSMC Technology Symposium: Process Status
At the recent TSMC Technology Symposium, various speakers gave details of the various TSMC processes. Since the rules of the technology symposium are that you can take notes but not record the presentation, nor photograph anything (and they don't hand out slides), the day is a bit like drinking from a firehose. Here's the important stuff I managed to note.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related Blogs
- TSMC OIP: Process Status
- Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
- Sensor Fusion and ADAS in TSMC Automotive Processes
- Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA