TSMC OIP: Process Status
Last week was TSMC's Open Innovation Platform Innovation Forum (aka OIP). Dave Keller welcomed everyone and then introduced Cliff Hou who gave the update on everything technical. Here's what he said. Or rather, here's what I think he said. I will give my usual caveat at the start of posts like this: TSMC does not allow photography, video, or recording the presentations, and they don't provide the slides. So this is entirely from the notes I took during the presentation.
I realize that this post is fairly dry and dense with numbers and dates, but since TSMC is far and away the largest foundry, these details are important, and they are not available anywhere else. You can try and find out from TSMC's website something specific like when N6 risk production is planned to start...but you will discover the information is not there.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related Blogs
- TSMC Technology Symposium: Process Status
- TSMC Financial Status Plus OIP Update!
- TSMC OIP: What to Do With 20,000 Wafers Per Day
- TSMC OIP and the Insatiable Computing Trend!
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA