TSMC OIP: On the Road to the Silicon Super Chip
October 7, 2013
SAN JOSE, Calif.--If you're the world's largest foundry, there's no slowing down, especially if you're roaring down the road to the "silicon wafer-based silicon super chip."
That was my take-away earlier this week (Oct. 1) listening to TSMC Vice President of R&D and CTO Dr. Jack Sun during TSMC's Open Innovation Platform® (OIP) event here at Cadence headquarters.
From 20nm system-on-chip (SoC) production, to the ramp of 16nm FinFETs, to 7- and 5-nm technologies in the distant future, and R&D and capacity investments in between, the pace of innovation at the Taiwanese company seems faster than ever.
To read the full article, click here
Related Semiconductor IP
- TSMC 3nm HBM3-8.6G PHY
- TSMC 5nm HBM3-8.4G PHY
- TSMC CLN7FF HBM3 PHY
- TSMC 3nm UCIe-A 32G Die to Die Interface
- TSMC 5nm UCIe-A 32G LP Die to Die Interface
Related Blogs
- Could TSMC be your next chip design cloud owner?
- TSMC OIP: What to Do With 20,000 Wafers Per Day
- TSMC at the 2015 Imagination Summit: optimized silicon IP for the IoT market
- DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps
Latest Blogs
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security
- Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
- Empowering your Embedded AI with 22FDX+