TSMC OIP: On the Road to the Silicon Super Chip
October 7, 2013
SAN JOSE, Calif.--If you're the world's largest foundry, there's no slowing down, especially if you're roaring down the road to the "silicon wafer-based silicon super chip."
That was my take-away earlier this week (Oct. 1) listening to TSMC Vice President of R&D and CTO Dr. Jack Sun during TSMC's Open Innovation Platform® (OIP) event here at Cadence headquarters.
From 20nm system-on-chip (SoC) production, to the ramp of 16nm FinFETs, to 7- and 5-nm technologies in the distant future, and R&D and capacity investments in between, the pace of innovation at the Taiwanese company seems faster than ever.
Related Semiconductor IP
- 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
Related Blogs
- Could TSMC be your next chip design cloud owner?
- TSMC OIP: What to Do With 20,000 Wafers Per Day
- TSMC at the 2015 Imagination Summit: optimized silicon IP for the IoT market
- DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?