The High-Speed Virtual Highway
September 23, 2011
By now it’s safe to say that complex, high-speed design is no longer a riddle….at least in theory.
We all know the end game. In its most fundamental form, isn’t it really a designer’s negotiation and compromise with the end user that comes down to action and reaction? We know users demand more and more applications to run simultaneously on their smart devices. We know that the underlying SoC in every device must sufficiently accommodate multiple data streams for each unique application. This is driving key architectural decisions for multi-core, multi-processor SoCs. Given that, how do we limit the amount of ‘compromise’ by the designer and give the customer more of that they want?
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related Blogs
- Driving the Future of High-Speed Computing with PCIe 7.0 Innovation
- The Zynq Virtual Platform: Not Just for Pre-Silicon
- Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform
- Virtual Platforms plus FPGA Prototyping, the Perfect Mix
Latest Blogs
- SiFive Celebrates 10 Years as Your Trusted Partner for RISC-V IP Innovation
- MIPI: Powering the Future of Connected Devices
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- Smarter SoC Design for Agile Teams and Tight Deadlines