The Zynq Virtual Platform: Not Just for Pre-Silicon
One of the biggest misconceptions about Virtual Platforms is that they are only useful for pre-silicon software development, and once a chip and board is ready they are quickly discarded. Even after boards are available, Virtual Platforms are valuable for software development.
Last week I was talking with an engineer at a company that is working on a new system design and has started Virtual Platform development. He told me that one of the software engineers was working on a demo to showcase their new operating system running on the target CPU. The software engineer had a reference board with the CPU and enough hardware to run the OS and show a demo application, but after a number of days struggling to get the software working to his satisfaction, they decided to try the SystemC Virtual Platform to see if any more information could be obtained. In less than 30 minutes the problem was found and fixed. The success was due to the visibility provided by the Virtual Platform, visibility that is not possible with a board. The lesson learned was that after hardware registers are programmed, it's very difficult to see what the system is doing.
To read the full article, click here
Related Semiconductor IP
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
Related Blogs
- Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform
- Arm Virtual Platform co-simulation solution accelerates SoC verification
- Virtual Platforms plus FPGA Prototyping, the Perfect Mix
- Virtual Platforms from Arm and Partners Available Now to Accelerate and Transform Automotive Development
Latest Blogs
- Area, Pipelining, Integration: A Comparison of SHA-2 and SHA-3 for embedded Systems.
- Why Your Next Smartphone Needs Micro-Cooling
- Teaching AI Agents to Speak Hardware
- SOCAMM: Modernizing Data Center Memory with LPDDR6/5X
- Bridging the Gap: Why eFPGA Integration is a Managed Reality, Not a Schedule Risk