Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
June 20, 2013
I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A recent article described Fujitsu Semiconductor's experience -- 35% better performance, 35% smaller area, 51% less power and faster turnaround time.
The benefits of moving up in abstraction are summarized by the following graph, which shows the leaps in productivity for every leap in abstraction:
To read the full article, click here
Related Semiconductor IP
- CXL 3 Controller IP
- PCIe GEN6 PHY IP
- FPGA Proven PCIe Gen6 Controller IP
- Real-Time Microcontroller - Ultra-low latency control loops for real-time computing
- AI inference engine for real-time edge intelligence
Related Blogs
- Software-Driven Hardware Verification
- "Great" Hardware Design in a Wireless World
- Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
- 4 Ways that Digital Techniques Can Speed Up Memory Design and Verification
Latest Blogs
- Arm Compute Platform at the Heart of Malaysia’s Silicon Vision
- IEEE 802.1ASdm-2024 Becomes an IEEE Standard – Advancing Time-Sensitive Networking
- Introducing the MIPS Atlas Portfolio for Physical AI
- Real-Time Intelligence for Physical AI at the Edge
- Moving the World with MIPS M8500 Real-Time Compute Solutions