Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
June 20, 2013
I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A recent article described Fujitsu Semiconductor's experience -- 35% better performance, 35% smaller area, 51% less power and faster turnaround time.
The benefits of moving up in abstraction are summarized by the following graph, which shows the leaps in productivity for every leap in abstraction:
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
Related Blogs
- Software-Driven Hardware Verification
- "Great" Hardware Design in a Wireless World
- Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
- 4 Ways that Digital Techniques Can Speed Up Memory Design and Verification