Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
June 20, 2013
I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A recent article described Fujitsu Semiconductor's experience -- 35% better performance, 35% smaller area, 51% less power and faster turnaround time.
The benefits of moving up in abstraction are summarized by the following graph, which shows the leaps in productivity for every leap in abstraction:
To read the full article, click here
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