Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
June 20, 2013
I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A recent article described Fujitsu Semiconductor's experience -- 35% better performance, 35% smaller area, 51% less power and faster turnaround time.
The benefits of moving up in abstraction are summarized by the following graph, which shows the leaps in productivity for every leap in abstraction:
To read the full article, click here
Related Semiconductor IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- 1.8V/3.3V GPIO With I2C Compliant ODIO in GF 55nm
- Verification IP for UALink
Related Blogs
- Software-Driven Hardware Verification
- Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
- 4 Ways that Digital Techniques Can Speed Up Memory Design and Verification
- Navigating the Era of Autonomous Design for Powerful Compute with Hardware