De-Mystifying SystemC: What is TLM?
In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day.
The first step is to separate the core functionality of the block from the way it interfaces to the system. So if you were designing an MPEG decoder, the decoding algorithm would be the core functionality. If it used AXI to communicate with the system, the AXI protocol would be the interface.
You can then describe the core using purely "untimed" SystemC. This is nice because you can focus on describing and verifying the algorithm itself, not worrying about how it will be implemented to meet the spec of a particular application. If you want to add some wait() statements to represent where you know you will need latency, that's fine. But you don't need to distribute them across logic, you can just stack them. That would be a "loosely-timed" model.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
- Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
- The Increasing Role of SystemC in System Design
- What Does SystemC Mean for Design and Verification?
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power