De-Mystifying SystemC: What is TLM?
In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day.
The first step is to separate the core functionality of the block from the way it interfaces to the system. So if you were designing an MPEG decoder, the decoding algorithm would be the core functionality. If it used AXI to communicate with the system, the AXI protocol would be the interface.
You can then describe the core using purely "untimed" SystemC. This is nice because you can focus on describing and verifying the algorithm itself, not worrying about how it will be implemented to meet the spec of a particular application. If you want to add some wait() statements to represent where you know you will need latency, that's fine. But you don't need to distribute them across logic, you can just stack them. That would be a "loosely-timed" model.
To read the full article, click here
Related Semiconductor IP
- USB 20Gbps Device Controller
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
Related Blogs
- Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
- Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
- The Increasing Role of SystemC in System Design
- What Does SystemC Mean for Design and Verification?
Latest Blogs
- Cadence Powers AI Infra Summit '25: Memory, Interconnect, and Interface Focus
- Integrating TDD Into the Product Development Lifecycle
- The Hidden Threat in Analog IC Migration: Why Electromigration rules can make or break your next tapeout
- MIPI CCI over I3C: Faster Camera Control for SoC Architects
- aTENNuate: Real-Time Audio Denoising