Synopsys TileLink Interconnect Verification IP for RISC-V SoCs
What is RISC-V?
Reduced Instruction Set Computer Architecture (RISC) is an instruction set architecture (ISA) which implies a basic bridge between hardware and software. RISC enables the communication between an assembly language programmer and a processor by defining a set of simple instructions that are combined to perform various complex instructions.
Both RISC and Complex Instruction Set Computer (CISC) approaches try to optimize a CPU’s processing time. In RISC, cycles required per instruction are reduced while instructions per program are increased. But in CISC, the number of instructions per program are reduced while cycles per instruction are increased.
Execution time = # of instructions per program X # of cycles per instruction
As a result, RISC is more of a software-based ISA as the software must take care of sending necessary simple instructions to execute an application. While CISC is a hardware-based ISA as instruction in CISC is complex and therefore needs complex instruction decoding.
RISC-V is an open standard instruction set architecture based on established RISC principles. Unlike most other ISA designs, RISC-V is provided under open-source licensing, which allows for broad use across the industry.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- Industry's First Verification IP for Arm AMBA CHI-G
- Industry's First Verification IP for PCIe 7.0
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- Skymizer Reduces Verification Cycles for AI Accelerator IP Development by 33% with Synopsys HAPS Prototyping
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power