Structured Asic Dies... Again

By SemiWiki

January 6, 2014

There has always been a dream that you could do a design in a cheap easy to design technology and then, if the design was a hit, press a button and instantly move it into a cheaper unit-price high volume design. When I was at VLSI in the 1980s we had approaches to make it easy to move gate arrays (relatively large die area) into standard cells almost automatically. Another approach was to try and get the design cost down and find a sweet spot between FPGAs and SoCs. LSI Logic had RapidChip structured-ASIC starting in the early 2000s, with pre-configured IP blocks and platforms that could quickly be programmed with just metal. Neither was successful.

This was especially attractive to FPGA vendors. By their nature, FPGAs are not very efficient in their use of silicon and so FPGA vendors such as Xilinx and Altera felt under pressure that if designs went into high volume manufacturing (HVM) that they should have a way to get the design into something more silicon efficient so they didn't lose the customer. Xilinx had a program called HardWire to do just this but it was killed off over a decade ago. Apparently they didn't lose the customers without such a program.

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