Are we on the verge of a new ASIC era? DARPA’s Nanowriter and practical e-beam lithography
January 26, 2011
The advent of gate arrays opened the gates of custom silicon for everycompany. Before that, only the really heavyweight players could afford the tools and training to create tailored ICs for their end products. The early gate arrays changed that situation by lowering costs to the point where custom silicon made sense in far more system designs. In a sense, we’re facing the same situation today. The cost of creating an SoC or ASIC in 65nm, 40nm, and now 32nm process technology has climbed to the tens of millions of dollars. It’s a game not everyone can play for a variety of reasons.
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Blogs
- Ivy Bridge: Intel's CPUs Gain a Generational Lithography Edge
- Adapteva's Epiphany Floating Point Processor Core: A Leading-Edge Lithography May Finally Open Doors
- TSMC on 450mm transition: Lithography key!
- DARPA Calls For 50X Improvement in SoC
Latest Blogs
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7
- UA Link PCS customizations from 800GBASE-R Ethernet PCS Clause 172