Are we on the verge of a new ASIC era? DARPA’s Nanowriter and practical e-beam lithography
January 26, 2011
The advent of gate arrays opened the gates of custom silicon for everycompany. Before that, only the really heavyweight players could afford the tools and training to create tailored ICs for their end products. The early gate arrays changed that situation by lowering costs to the point where custom silicon made sense in far more system designs. In a sense, we’re facing the same situation today. The cost of creating an SoC or ASIC in 65nm, 40nm, and now 32nm process technology has climbed to the tens of millions of dollars. It’s a game not everyone can play for a variety of reasons.
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Blogs
- Ivy Bridge: Intel's CPUs Gain a Generational Lithography Edge
- Adapteva's Epiphany Floating Point Processor Core: A Leading-Edge Lithography May Finally Open Doors
- TSMC on 450mm transition: Lithography key!
- DARPA Calls For 50X Improvement in SoC
Latest Blogs
- Why What Where DIFI and the new version 1.3
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware