How much SRAM proportion could be integrated in SoC at 20 nm and below?
Once upon a time, ASIC designers were integrating memories in their design (using a memory compiler being part of the design tools provided by the ASIC vendor), then they had to make the memory observable, controllable… and start developing the test program for the function, not a very enthusiastic task (“AAAA” and “5555” and other vectors), look for the test coverage, and try to be creative to reach the expected 99,99% magic number. I agree that this was long time ago, but when looking back to this old time, you realize how powerful is DesignWare Self-Test and Repair (STAR) Memory System from Synopsys, initially developed by Virage Logic. Today we are talking about the version 5 of the tool. Moreover, since the year 2000’s, most of the ASIC vendors are externally sourcing the SRAM compiler (to Virage Logic at that time…), ASIC designer is taking benefit of faster, denser memories with Built-In-Self-Test (BIST) integrated.
To read the full article, click here
Related Semiconductor IP
- Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Dual Rail SRAM Globalfoundries 22FDX
- SRAM Test and Repair Solution
- SRAM Test and Repair Solution
- SRAM Test Solution
Related Blogs
- Understanding USB IP and Its Role in SOC Integration
- 2024 Set The Stage For NoC Interconnect Innovations In SoC Design
- NoC for faster SoC integration
- Experts At The Table: SoC Integration Mistakes
Latest Blogs
- Why Anti-tamper Sensors Matter: Agile Analog and Rambus Deliver Comprehensive Security Solution
- Automotive Ethernet with Comcores – Safety, Quality and ASIL certification of IP
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform