Experts At The Table: SoC Integration Mistakes
February 13, 2014
First of three parts: What’s missing; common problems and how to avoid them; what’s behind these errors and re-spins; proximity effects; communication breakdowns.
Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion.
Related Semiconductor IP
- Securyzr™ neo Core Platform
- 112G Multi-SerDes
- SHA3 Cryptographic Hash Cores
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
Related Blogs
- SoC Integration Mistakes
- NoC for faster SoC integration
- Bluetooth 5 IP is Ready for SoC Integration
- Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application
Latest Blogs
- Why Anti-tamper Sensors Matter: Agile Analog and Rambus Deliver Comprehensive Security Solution
- Automotive Ethernet with Comcores – Safety, Quality and ASIL certification of IP
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform