Spec-based Coverage Closure with Synopsys VIP
January 30, 2015
Here, Synopsys R&D Director Bernie DeLay talks about achieving coverage closure for protocol compliance checking and integration testing by utilizing the built-in verification plans and functional coverage provided with VC VIP.
He describes configuration-aware coverage: how it correlates with the user’s specification
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Blogs
- Reducing Manual Effort and Achieving Better Chip Verification Coverage with AI and Formal Techniques
- Coverage Models - Filling in the Holes for Memory VIP
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- How Qualcomm Accelerated Coverage Closure with AI-Driven Verification
Latest Blogs
- A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library
- FPGAs vs. eFPGAs: Understanding the Key Differences
- UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
- RT-Europa: The Foundation for RISC-V Automotive Real-Time Computing
- Arm Flexible Access broadens its scope to help more companies build silicon faster