Reducing Manual Effort and Achieving Better Chip Verification Coverage with AI and Formal Techniques
Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the chip development cycle. Coverage lies at the very heart of this process, providing the best way to assess verification progress and determine where to focus further effort. Code coverage of the register transfer level (RTL) chip design, functional coverage as specified by the verification team, and coverage derived from assertions are combined to yield a single metric for verification thoroughness.
Coverage goals are usually quite high (95% or more) and hard to achieve. Chip verification engineers spend weeks or months trying to hit unreached coverage targets to ensure that the design is thoroughly exercised and bugs are not missed. Traditionally this has involved a lot of manual effort, consuming valuable human resources and delaying project schedules. Fortunately, in recent years several powerful techniques have been developed to automate the coverage process, achieve faster coverage closure, and end up with higher overall coverage.
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