Simplifying the Usage of UVM Register Model
When I began using UVM RAL, I could not understand what the UVM base class library had to say about updating the values of desired value and mirror value registers. I also felt that the terms used do not reflect the intent precisely. After spending some time, I came up with a table which helped me to understand the behavior of register model APIs, and how best they can be called.
Before I introduce the table, let us take a look at the process of creating the register model:
- Creating the register format specification
- Converting the specification into UVM register model
- Using the register model
To read the full article, click here
Related Semiconductor IP
- PUF-based Post-Quantum Cryptography (PQC) Solution
- OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
- HBM4 PHY IP
- 10-bit SAR ADC - XFAB XT018
- eFuse Controller IP
Related Blogs
- From DIY To Advanced NoC Solutions: The Future Of MCU Design
- Guarding against the threat of clock attacks with analog IP
- Arm Compute Platform at the Heart of Malaysia’s Silicon Vision
- Imagination and Renesas Redefine the Role of the GPU in Next-Generation Vehicles