Simplifying the Usage of UVM Register Model
January 6, 2015
When I began using UVM RAL, I could not understand what the UVM base class library had to say about updating the values of desired value and mirror value registers. I also felt that the terms used do not reflect the intent precisely. After spending some time, I came up with a table which helped me to understand the behavior of register model APIs, and how best they can be called.
Before I introduce the table, let us take a look at the process of creating the register model:
- Creating the register format specification
- Converting the specification into UVM register model
- Using the register model
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Navigating the Future of EDA: The Transformative Impact of AI and ML
- The Pillars of ReRAM Success
- DAC 2024 - Showcasing the future of RISC-V through EDA
- DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers
Latest Blogs
- Evolution of CXL PBR Switch in the CXL Fabric
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success