MoSys combines design, process and test to break the 2 billion accesses per second barrier

By _EETimes Blog

April 23, 2012

MoSys has created a new serial memory—the Bandwidth Engine IC—that leverages a highly efficient 10G serial interface and innovative architecture to perform over 2 billion memory accesses per second. This access rate is necessary to support data rates required by 100GE (Gigabit Ethernet) and 100Gb/s aggregate line cards. The Bandwidth Engine IC contains intelligence in ALUs and memory architectures that accelerates networking operations such as statistics and was designed for use in applications where high data speeds, 10-year expected lifetimes, and government mandated power reductions create restrictive specifications. Bandwidth Engine distinguishes itself relative from traditional networking devices by putting the emphasis on fast, intelligent access which works well in the packet classification applications. This required MoSys to use a highly collaborative design approach. To achieve this access rate, a combination of exacting product definition, tightly designed RTL code, a high speed and low-latency SerDes, the core 1T-SRAM technology developed by MoSys, and innovative layout and packaging design were employed. The result is a device which eases SoC packaging and system design challenges by using a high speed serial interface.  Overall system performance is increased while power and cost are reduced by the consolidation of banks of traditional memory devices into one Bandwidth Engine.

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