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Compare 877 IP from 67 vendors (1 - 10)
  • 1-56Gbps Serdes - 7nm (Multi-reference Clock)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (Ultra Low Latency)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (Area-optimized)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-112Gbps Serdes - 7nm
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (PPA-optimized)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
    • A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
    • This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
    • Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
    Block Diagram -- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
  • Programmable Low Power SERDES Receiver on TSMC CLN65LP
    • Programmable SERDES analog receiver that supports 0.6 to 3.75 Gbps standard serial protocols
    • Compact form factor – 0.1 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.8 mW/Gbps including termination
    • Minimal latency – 4 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 11+ Gbps standard serial protocols
    • Compact form factor – 0.104 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.8 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN28HPL
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.095 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.6 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
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