High-speed LVDS (SERDES) transceiver with up to 8 serial data lanes, generic data width and integrated asynchronous FIFO. Ideal for standard LVDS links such as Channel-link®, Camera-link®, FPD-link®, FlatLink®, MIPI etc.
Capable of data rates of up to 500 MBits/s per lane on basic FPGA devices and 1 Gbits/s+ on higher-end FPGAs.
High-Speed LVDS (SERDES) Transceiver
Overview
Key Features
- Separate Tx/Rx pair
- Up to 8 serial data lanes
- Parallel data widths up to 128-bits wide
- Parallel-to-serial mux ratio up to 16:1
- Fully configurable clocking
- Data rates of up to 1 Gbits/s per lane
- Integrated asynchronous FIFOs
- Frequency mismatch error detection
- Bitwise data alignment at receiver
- No receiver source clock required
- Simple to implement using CAT5E cable
- Supports industry standards such as MIPI,
- Camera-link®, Channel-link®, FPD-link® etc.
- Compatibility with commercial LVDS ICs
- Examples: SN65LVDS*, SN75LVDS*, DS90CR*,
- DS90UR* and THC63LVD* series ICs
Benefits
- Technology independent soft IP Core
- Suitable for FPGA, SoC and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Block Diagram

Deliverables
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Technical Specifications
Foundry, Node
All (with some customization)
Availability
Immediate
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