Scaling AI Infrastructure with Next-Gen Interconnects
April 29, 2025
At the recent IPSoC Conference in Silicon Valley, Aparna Tarde gave a talk on the importance of Next-Gen Interconnects to scale AI infrastructure. Aparna is a Sr. Technical Product Manager at Synopsys. A synthesis of the salient points from her talk follows.
Key Takeaways
- The rapid advancement of AI is reshaping data center infrastructure requirements, demanding immense compute resources and unprecedented memory capacity.
- Efficient XPU-to-XPU communication is crucial, requiring high-bandwidth, low-latency, and energy-efficient interconnects for large-scale compute clusters.
- New communication protocols and interfaces like UALink and Ultra Ethernet are essential for scaling AI performance and accommodating distributed AI models.
- The shift from copper to optical links and the adoption of Co-Packaged Optics (CPO) are key to addressing bandwidth challenges in AI infrastructure.
- Multi-die packaging technologies are becoming mainstream to meet AI workloads' demands for low latency, high bandwidth, and efficient interconnects.
Related Semiconductor IP
- PCIe Gen 7 Verification IP
- PCIe Gen 6 Phy
- PCIe Gen 6 controller IP
- PCIe Gen 5 - Validates high-speed designs, ensuring compliance and error-free performance
- PCIe Gen 4 - Enables high-speed verification, error handling, and protocol compliance
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- Ultra Ethernet Consortium Set to Enable Scaling of Networking Interconnects for AI and HPC
- How Synopsys and NVIDIA Are Accelerating Semiconductor Scaling in the AI Age
- Powering the Next Wave of AI Inference with the Rambus GDDR6 PHY at 24 Gb/s