Renesas Collaborates on Large Language Model Generative AI Chip Design
Renesas and Cadence have been collaborating for several years, combining their expertise to drive advancements in chip design. Their partnership has been instrumental in creating innovative solutions that address the complex challenges faced by chip designers in today's rapidly evolving technological landscape. Most recently, the collaboration has focused on generative AI and its impact on semiconductor quality and design team productivity. They are also early adopters of Cadence Generative AI solutions, including Cadence Cerebrus for chip implementation, Verisium AI-driven verification, and the Cadence Joint Data and AI (JedAI) Platform.
The world of generative AI is evolving rapidly! I'm now a regular user of ChatGPT for various projects at work and home. At Cadence, we are seeing a dramatic uptick in adopting our JedAI generative AI solution. We recently announced the industry's first large language model (LLM) for chip design (a proof of concept project named ChipGPT) and the OrCAD X Platform for PCB design, optimized for small and medium businesses
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Blogs
- Chip Design Industry Reaches an AI Inflection Point
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer
- Different By Design: Customized Processors Help Build Chip Differentiation
Latest Blogs
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7
- UA Link PCS customizations from 800GBASE-R Ethernet PCS Clause 172