70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC
The title for this blog entry comes from a statement made early in a presentation on SoC design given at this week’s International SoC Conference in Newport Beach, California. The speaker was Cormac O’Sullivan from the S3 Group in Cork, Ireland. O’Sullivan is the RF and Mixed Signal Engineering Team Lead and S3 is a design house specializing in RF and mixed-signal SoC design. The official title of his presentation was “RF SoC Design Flow.”
Why worry about RF and mixed-signal SoC design?
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- Six Issues that will Inhibit Profitable Growth in 2010 - Be Ready
- Real Number Model Development and Application in Mixed-Signal SoC Verification
- Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM
- IP Roundtable, Part 6: Integration Issues Ahead
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power