Real Number Model Development and Application in Mixed-Signal SoC Verification
With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification, characterized by performance and accuracy tradeoffs -- thus making AMS verification the biggest challenge facing verification engineers today.
To read the full article, click here
Related Semiconductor IP
- 12-Bit 1 MS/s DAC with voltage output on AMS C18
- 16 Bit 10 kS/s Incremental Delta-Sigma ADC on AMS H35
- 10 Bit 40 MS/s Pipeline ADC on AMS C18
- 600MHz General Purpose PLL for ams 180nm
- 11-bit, 2MSPS SAR ADC/DAC - 11-bit, 15MSPS, Hybrid SAR - AMS 0.35 um
Related Blogs
- 70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC
- T&VS delivers Emulation and Validation services for Mobile SoC
- SoC verification through Managed service
- T&VS provides end-to-end DFT solution for Consumer SoC
Latest Blogs
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility