Real Number Model Development and Application in Mixed-Signal SoC Verification
April 9, 2012
With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification, characterized by performance and accuracy tradeoffs -- thus making AMS verification the biggest challenge facing verification engineers today.
To read the full article, click here
Related Semiconductor IP
- 128MHz PLL for ams 0.18u Processes
- 600MHz General Purpose PLL for ams 180nm
- 11-bit, 2MSPS SAR ADC/DAC - 11-bit, 15MSPS, Hybrid SAR AMS 0.35 um
Related Blogs
- In Mixed-Signal SoC Verification, Say Good-bye to the Black Box Problem
- T&VS delivers Emulation and Validation services for Mobile SoC
- SoC verification through Managed service
- T&VS provides end-to-end DFT solution for Consumer SoC