Real Number Model Development and Application in Mixed-Signal SoC Verification
April 9, 2012
With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification, characterized by performance and accuracy tradeoffs -- thus making AMS verification the biggest challenge facing verification engineers today.
To read the full article, click here
Related Semiconductor IP
- 12-Bit 1 MS/s DAC with voltage output on AMS C18
- 16 Bit 10 kS/s Incremental Delta-Sigma ADC on AMS H35
- 10 Bit 40 MS/s Pipeline ADC on AMS C18
- 600MHz General Purpose PLL for ams 180nm
- 11-bit, 2MSPS SAR ADC/DAC - 11-bit, 15MSPS, Hybrid SAR - AMS 0.35 um
Related Blogs
- T&VS delivers Emulation and Validation services for Mobile SoC
- SoC verification through Managed service
- T&VS provides end-to-end DFT solution for Consumer SoC
- Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application
Latest Blogs
- Physical AI at the Edge: A New Chapter in Device Intelligence
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7