Want a peek at a possible Qualcomm 3D IC roadmap?
April 11, 2012
“3D IC test wafers will run this year and high-volume 3D IC manufacturing will start in 2013,” concluded Riko Radojcic at the end of his EDPS keynote on 3D ICs held in Monterey, California last Friday. Radojcic is Qualcomm’s Director of Engineering, so he just might know something about the state of 3D IC assembly although he’s not necessarily referring to Qualcomm in the above statement. His concluding remarks came at the end of an hour’s worth of hard-earned 3D IC assembly and design insights that Radojcic has assembled at Qualcomm.
To read the full article, click here
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- Semicon West: The Roadmap is 3D IC
- Qualcomm, AMD head top 25 fabless IC suppliers for 2009; Taiwan firms finish strong!
- What's driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?
- Qualcomm: Scaling down is not cost-economic anymore - so we are looking at true monolithic 3D
Latest Blogs
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status