What's driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?
April 14, 2011
The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul Deokar, a Product Marketing Director at Cadence. Among other things, Deokar is responsible for 3D IC design tools.
Here’s what Deokar discussed in his presentation:
Related Semiconductor IP
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- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
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