What's driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?
The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul Deokar, a Product Marketing Director at Cadence. Among other things, Deokar is responsible for 3D IC design tools.
Here’s what Deokar discussed in his presentation:
Related Semiconductor IP
- HBM4 PHY IP
- 10-bit SAR ADC - XFAB XT018
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
Related Blogs
- ICCAD Keynote: Design of Secure Systems - Where are the EDA Tools?
- Want a peek at a possible Qualcomm 3D IC roadmap?
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Intel Calls for 3D IC
Latest Blogs
- Epson Achieves 50% Energy Efficiency with QuickLogic eFPGA
- Industry’s First Verification IP for Arm AMBA DTI-H
- 2025 Year in Review: Design Wins, Advanced Nodes, and Expanding Markets
- JESD204 Frame Mapping explained from converter samples to lanes
- Arm in the agentic era: Scaling the converged AI data center