What's driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?
April 14, 2011
The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul Deokar, a Product Marketing Director at Cadence. Among other things, Deokar is responsible for 3D IC design tools.
Here’s what Deokar discussed in his presentation:
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related Blogs
- 3D chips: design tools
- ICCAD Keynote: Design of Secure Systems - Where are the EDA Tools?
- Which Direction for EDA - 2D, 3D, or 360?
- 3D chips: IBM server
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?