Introducing PCIe's Integrity and Data Encryption Feature (IDE)
The Integrity and Data Encryption (IDE) was published in PCIe (Peripheral Component Interconnect Express) version 6.0, and it was created as a tool to protect the communication between the different devices of the PCIe topology root complex (RC), switch (SW), and endpoint (EP). The IDE layer is a new layer that was inserted between the transection layer and data link layer with the goal of protecting against threats from physical attacks on the link. The IDE will use a cryptography mechanism to encrypt all data sent for both sides.
The IDE feature has two types of streams: the link IDE stream and the selective IDE stream. The link stream, in yellow, is a security channel in the link, and the selective stream, in blue, is a security channel between devices, not necessarily in the same link.
To read the full article, click here
Related Semiconductor IP
- AXI Bridge with DMA for PCIe IP Core
- PCIe Gen 7 Verification IP
- PCIe Gen 6 Phy
- PCIe Gen 6 controller IP
- PCIe GEN6 PHY IP
Related Blogs
- Verification of Integrity and Data Encryption (IDE) for CXL Devices
- Partial Header Encryption in Integrity and Data Encryption for PCIe
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- Big Innovations Double the Data Rate to 64 GT/s with PCIe 6.0
Latest Blogs
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach
- UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC