On-chip networks: Future of SoC design
Selection of the right on-chip network is critical to meeting the requirements of today’s advanced SoCs. There is easy IP integration with IP cores from many sources with different protocols, and an UVM verification environment.
John Bainbridge, staff technologist, CTO Office, Sonics Inc., said that it optimizes the system performance. Virtual channels offer efficient resource usage – saves gates and wires. The non-blocking network leads to an improved system performance. There are flexible topology choices with optimal network to match requirements.
Power management is key with advanced system partitioning, and an improved design flow and timing closure. Finally, the development environment allows easy design capture and has performance analysis tools.
For the record, there are several SoC integration challenges that need to be addressed, such as IP integration, frequency, throughput, physical design, power management, security, time-to-market and development costs.
To read the full article, click here
Related Blogs
- From DIY To Advanced NoC Solutions: The Future Of MCU Design
- Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
- Want to see the future of low-power SoC design? Have a look into Gary Smith’s crystal ball
- Hogan explains the fundamental market drivers for On-Chip Networks
Latest Blogs
- Evolution of CXL PBR Switch in the CXL Fabric
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success