Want to see the future of low-power SoC design? Have a look into Gary Smith’s crystal ball
April 12, 2012
Last week at the Electronic Design Process Symposium held in Monterey, EDA analyst Gary Smith put together a session on low-power design and he prefaced the other presentations with one of his own showing where he though the improvements in SoC power consumption would be coming from through the year 2026. Smith charts a lot of data for the ITRS (International Technology Roadmap for Semiconductors) and his charting is based on his own research plus a consensus gathering process. In his presentation, Smith first look back into the past, listing 11 advances from 1996 through 2007 that have reduced SoC operating power including:
To read the full article, click here
Related Semiconductor IP
- Temperature Glitch Detector
- Clock Attack Monitor
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
Related Blogs
- SOC Design Techniques that Enable Autonomous Vehicles
- An Easy Path to Bluetooth 5-enabled SoC Design
- New Research Enablement Kit: SoC Design and Prototyping
- The Arm Ecosystem: More than Just an Ecosystem, it's Oxygen for SoC Design Teams