NVM Express® Modifications for I3C: Improved Out-of-Band Manageability of NVMe® SSDs
To keep your data centers running optimally, you must have an out-of-band management port on each NVM Express® (NVMe®) SSD used to discover, configure, monitor and update each NVMe SSD attached to a platform regardless of your platform’s OS and health. Historically, this path has been achieved using PCI Express® (PCIe®) Vendor Defined Message over the NVMe SSD’s main PCIe bus or sideband using muxed SMBus technology. The faster solution is to manage NVMe SSDs using PCIe VDMs, but not all platforms have a PCIe VDM path or the PCIe bus may be unavailable due to PCIe link-down conditions. The sideband SMBus mux path is always available but can get maxed out by the ever-increasing size of firmware updates, security traffic and telemetry logs.
How is NVM Express helping to address these sideband security issues and bandwidth demands? We are pleased to introduce the NVMe technology modifications for Improved Inter Integrated Circuit (I3C). Our technical work groups created these modifications to improve sideband bandwidth, latency, robustness, security and efficiency for NVMe Management Interface (NVMe-MI™) technology, while also maintaining backwards compatibility with the SMBus interface. In this blog, I explore how I3C enhances sideband NVMe technology to make it your ideal data center storage sideband management path.
Related Semiconductor IP
- NVM Express (NVMe) Controller (compliant with NVMe 1.4 Base Specification)
- Universal NVM Express Controller (UNEX)
- NVM Express IP Core
Related Blogs
- Watch out SSDs, here comes the NVM Express!
- NVM Express: pervasion of PCI Express in SSD based storage
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
- Cadence's NVM Express: fruit from subsystem IP based strategy
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