Cadence's NVM Express: fruit from subsystem IP based strategy
July 4, 2012
If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application Processor. Are we naïve if we think the next step should be subsystem IP? It would really make sense to use an IP aggregation, organized in such a way that it could support a specific application!
Related Semiconductor IP
- NVM Express (NVMe) Controller (compliant with NVMe 1.4 Base Specification)
- Universal NVM Express Controller (UNEX)
- NVM Express IP Core
Related Blogs
- Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
- NVMe 2.0 Specifications: Support for Fabrics and Multi-Domain Subsystems
- Watch out SSDs, here comes the NVM Express!
- NVM Express: pervasion of PCI Express in SSD based storage
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?