This macro-cell is a general purpose, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) subsystem. The DAC employs a hybrid architecture, using 6-bit resistive and 5-bit capacitive sub-DACs.
It is a standard part, enabling multiple system utilizations. The core operates in 11-bit linear mode and uses one 3.3V analog and one 3.3V digital supplies.
The core includes built-in sample-and-hold functionality.
