MIPI UniPro: Major Differentiating Features, Benefits and Verification Challenges
MIPI UniPro is a recent addition to mobile chip-to-chip interconnect technology. It’s got many useful features to meet the requirements of mobile applications. That’s perhaps why Google’s Project Ara has selected MIPI UniPro and MIPI M-PHY as its backbone interconnects.
In this blog post, we describe three differentiating features, benefits and their verification challenges. All the discussion is referenced to MIPI UniPro 1.6.
- Achieving Low power consumption through Power mode changes and hibernation
- Flexibility in chip-to-chip lane routing through Physical Lane mapping
- Enhanced QoS through CPort arbitration & Data link layer pre-emption
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Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- MIPI UniPro through eyes of PCI Express
- MIPI UniPro: Comprehensive Verification Checklist
- MIPI Unipro Transport Layer (L4) - An Introduction
- Technical Comparison: MIPI UniPro 1.6 vs MIPI UniPro 1.41