M-PCIe - The New Big Thing from MIPI Alliance and PCI-SIG
If you’re reading this, you must have heard about the M-PCIe specification that has just been announced by two very important standardization bodies in the semiconductor industry—MIPI Alliance and PCI-SIG. According to the press release that was released during the PCI-SIG event last month, “M-PCIe specification provides uncompromised scalable performance while delivering a consistent user experience across multiple mobile platforms.” This sounds very appealing, but exactly does it mean to the mobile SoC developers?
As I wrote in my previous post, the MIPI Alliance is known for the introduction of over 30 specifications targeted for mobile platforms, and has managed to do this in just 10 years. Certainly, 10 years is a lot of time, and mobile market is the fastest growing segment of the semiconductor industry, but still the number is impressive. Even more impressive is the fact that these specs have been adopted by the major players in the market, and thus have made their way into pretty much every mobile device there is.
Related Semiconductor IP
- PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x1, North/South (vertical) poly orientation
Related Blogs
- Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences
- Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon 24
- Announcing the launch of CHERI Alliance: A unified front against digital threats
- Is the Common Platform Alliance a credible competitor to TSMC?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?