Lowering Risks with RISC-V
Reduced Instruction Set Computing Five (RISC-V) is an open Instruction Set Architecture (ISA) designed with small, fast, and low-power real-world implementations in mind. It describes the way in which software talks to an underlying processor, in a manner similar to the x86 ISA for Intel/AMD processors and the ARMv8 ISA for the latest ARM processors. However, unlike x86 ISA and ARMv8 ISA, the RISC-V ISA is open source. Any party can build a processor that using RISC-V. Not only simply processing architecture, but with a substantial body of supporting software, RISC-V can be freely used by anyone, for any purpose, and useful in a wide range of devices.
In the wake of Meltdown, Spectre, and Foreshadow exploits found in modern CPUs, people are beginning to realize that modern CPUs may be designed for performance first, safety second. In Rambus’ CryptoManager Root of Trust, the RISC-V core is located on the same silicon as the general processor, but physically separated by a secure boundary. It can run algorithms and processes within that secure boundary to protect against a wide range of attacks, including side-channel attacks, and protect against software vulnerabilities and exploits. It can also prevent device cloning.
To read the full article, click here
Related Semiconductor IP
- All-In-One RISC-V NPU
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- RISC-V CPU IP
- Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
Related Blogs
- Expanding the RISC-V Ecosystem, with PX5, IAR and SiFive
- Unlock the Possibilities with HiFive Unmatched RISC-V Development Boards
- Effectively hiding sensitive data with RISC-V Zk and custom instructions
- From vision to reality in RISC-V: Interview with Karel Masarik
Latest Blogs
- Upgrade the Raspberry Pi for AI with a Neuromorphic Processor
- Securing The Road Ahead: MACsec Compliant For Automotive Use
- Beyond design automation: How we manage processor IP variants with Codasip Studio
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies