Increasing Verification Productivity Through Automation of Functional Coverage Management
Functional coverage plays a very important role in verifying the completeness of a design. However customizing a coverage plan for different chips, users, specification versions etc is a very tedious process especially when dealing with a complex design.Quite often a verification engineer needs to customize the coverage plan. Customization might be required as the coverage plan can vary amongst multiple users. Additionally, users might need to reflect regular updates in specifications in the coverage plan. Making all these changes in the source coverage code leads to conflicts and confusion amongst different users and projects. Managing the above stated issues is one of the most challenging and time consuming tasks a verification engineer faces today.
This blog/article describes a simple methodology which addresses all the above issues, using the concept of inheritance. This customization methodology can be used across all protocols.
Related Semiconductor IP
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
Related Blogs
- Functional Coverage Plan Management - What's the Secret Sauce?
- Leveraging AI to Optimize the Debug Productivity and Verification Throughput
- The Role of Coverage in Formal Verification, Part 1 of 3
- Is Your Functional Coverage Stuck at 70%?
Latest Blogs
- Area, Pipelining, Integration: A Comparison of SHA-2 and SHA-3 for embedded Systems.
- Why Your Next Smartphone Needs Micro-Cooling
- Teaching AI Agents to Speak Hardware
- SOCAMM: Modernizing Data Center Memory with LPDDR6/5X
- Bridging the Gap: Why eFPGA Integration is a Managed Reality, Not a Schedule Risk