How to Verify Performance of Complex Interconnect-Based Designs?
July 15, 2019
With more and more SoCs employing sophisticated interconnect IPs to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions:
While your interconnect subsystem might have a correct functionality, are you starving your IP functions of the bandwidth they need? Are requests from latency-critical initiators processed on time? How can you ensure that all applications will receive the desired bandwidth in steady-state and corner use-cases?
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