Interconnect IP
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578
IP
from 75 vendors
(1
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10)
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UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Emerging Standard Knowledge
- Flexibly Configurable
- Best in Class PPA
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FlexNoC 5 Interconnect IP
- Physical Awareness for faster timing closure
- Higher margins
- Fewer wires
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High speed NoC (Network On-Chip) Interconnect IP
- High Performance
- Low Power Consumption
- Smaller Area
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Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
- Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
- High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
- Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
- Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
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Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N5 X24, North/South (vertical) poly orientation
- Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
- High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
- Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
- Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
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AXI Multilayer Interconnect
- Arbitrary number of master ports
- Arbitrary number of slave ports
- User-defined bit width for: AXI Data bus (9-1024), AXI Address bus (1-64), AXI Master and slave ID signals (1-64).
- User-defined slave to master mapping. Slaves access can be disabled to one or more masters.
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AHB Multilayer Interconnect
- Arbitrary number of AHB-Lite master ports
- Full AHB masters can also be connected
- Arbitrary number of AHB slave ports
- User-defined slave to master mapping
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Low Latency Interconnect for AI/ML (GreenIPCore Shared Multi Memory Integration Controller (SMMIC))
- Multiple Slave side interfaces supported configurable for each port.
- Standard AMBA interfaces AXI, AHB and APB Supported.
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AXI Interconnect Fabric
- AMBA® AXI-4 Compatible
- Multiple AXI Channels
- Off the shelf core supports 4 Masters and 8 Slaves
- Arbitration is done at each slave
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Serial Peripheral Interconnect Master & Slave Interface Controller
- Run-time programmable Master or slave mode operation.
- Bit rates generated in Master mode: ÷2, ÷4, ÷6, ÷8, ÷10, ÷12, ...÷512 of the system clock.
- Bit rates supported in Slave mode: fSCK ≤ fSYSCLK ÷4
- Support for 1,2,4 or unlimitted bytes multi-byte frame data transfers, run-time programmable.
