How to Verify Complex PIPE Interface Based PHY Designs?

By _Cadence - Cadence IP Blog

November 22, 2022

High-end SOC architectures today requiring more area and higher speed to transfer and process data. To fulfill this requirement, protocol such as PCIe, USB, DP, SATA and USB4 are regularly being updated. Most critical part of the high-speed interface is the Physical (PHY) layer of the protocol where the actual signaling happens. In addition to signaling, the PHY also takes care of some of the processing to reduce errors in transmission and error recovery. This makes the PHY design very complex as it involves both high speed digital logic and analog circuitry. Usually the rest of the protocol can be implemented purely using digital logic. Hence the IP/SoC developers develop the PHY separately from the rest of the protocol logic. This will allow both developments to happen in parallel and independently. This created a need for a standard interface between PHY module and rest of the protocol logic. The PIPE specification effectively defines this interface. One of the intents of the PIPE specification is to accelerate the development of PCIe, SATA, USB, USB4, DP MAC. The most recent changes in the PIPE is SerDes architecture and low pin count interface. The PIPE specification has upgraded to version 6.1.1 to match the latest protocol specifications of PCIe, DP and USB4.

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