GloFo's 12nm FD-SOI: why it makes headlines in China
As you've probably seen in (excellent!) recent semiwiki postings by Eric Esteve and Scotten Jones, 12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap. Eric and Scotten did a great job of putting many things in perspective. But this is a big piece of news, so here I propose looking at it from yet another perspective, adding a few details from GloFo's press releases, and showing some supporting slides from their presentations at the FD-SOI Forum in Shanghai last month. Why the italics? Read on.
First, just to be clear, GloFo's target with 12FDX, as it's called, is intelligent, connected systems. They say it's beating 14/16nm FinFET on performance, power consumption (by 50%) and cost. Add back bias and it beats 10nm FinFET. Customer product tape-outs are expected to begin in the first half of 2019. That should put them in a pretty sweet spot for the leading edge of their target customers doing those “intelligent, connected systems”.
To read the full article, click here
Related Semiconductor IP
- Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
- eFPGA on GlobalFoundries GF12LP
- ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
- Wide Range Programmable Integer PLL on GLOBALFOUNDRIES 28SLPE
- Wide Range Programmable Integer PLL on GLOBALFOUNDRIES 130N
Related Blogs
- FD-SOI, an Opportunity for China?
- GlobalFoundries Endorse ST/LETI FD-SOI 22nm!
- GlobalFoundries FD-SOI. Yes, It's True
- GlobalFoundries 22nm FD-SOI: What Happens When
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA