Will verification challenges overwhelm FPGA design?

By _EDA360 Insider

October 20, 2010

EETimes just published a blog titled “FPGAs advance, but verification challenges increase,” written by GateRocket’s president and CEO Dave Orecchio. The article makes the point that FPGAs are rapidly losing their “easy-to-use” market positioning because, to put it quite simply, they are now reaching complexity levels that make verification efforts difficult. Just as difficult as when ASICs evolved into SoCs more than a decade ago (and then MPSoCs) and created similar problems. Increasing FPGA complexity is actually a very good thing, because it means that you can use FPGAs to do more things. Meanwhile, ASIC-based SoCs continue to evolve with process technology advances and they can also do more things—many, many more things. However, design complexity brings problems regardless of the implementation technology used and certainly verification at all design levels is one of the thorniest problems to come along.

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