Doing JEDEC or MIPI IP Verification? Here Are Some Test Plans
March 24, 2014
JEDEC and MIPI technologies are really HOT this year! MIPI has built a formidable "engine" in MIPI UniPro and MIPI M-PHY - that can be harnessed by technologies like JEDEC UFS, MIPI CSI-3 and MIPI DSI-2.
Given the popularity of these technologies, it is important for IP developers to race till the finish line. We have taken some of the stress out of IP development by providing Free Downloadable Test Plans for select MIPI and JEDEC protocols. Get a head start over competition!
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- How did JEDEC UFS beat the MIPI CSI3 and DSI2 in adoption race?
- Cadence Announces the First MIPI I3C Verification IP!
- MIPI UniPro: Major Differentiating Features, Benefits and Verification Challenges
- Accelerate your MIPI CSI-2 Verification with a Divide and Conquer Approach