Demonstrating PCIe 6.0 Equalization Procedure
The Link equalization procedure enables components to adjust the Transmitter and the Receiver setup of each Lane to improve the signal quality and meet the requirements, when operating at 8.0 GT/s and higher data rates. All the Lanes that are associated with the LTSSM (i.e., those Lanes that are currently operational or may be operational in the future due to Link Up-configure) must participate in the Equalization procedure.
Components must arrive at the appropriate Transmitter setup for all the operating conditions and data rates they will encounter.
The equalization procedure can be initiated either autonomously or by software. It is strongly recommended that components use the autonomous mechanism. However, a component that chooses not to participate in the autonomous mechanism must have its associated software to ensure that the software-based mechanism is applied.
To read the full article, click here
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related Blogs
- PCIe 5.0 Equalization Modes: Reducing Link Bring-Up Time
- PCIE 6.0 vs 5.0 - All you need to know
- Big Innovations Double the Data Rate to 64 GT/s with PCIe 6.0
- Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0