RISC-V Software: Great Progress in 2024 and Much More Ahead in 2025

By Ian Ferguson, SiFive Senior Director

January 28, 2025

As RISC-V technology broadens its reach from broad adoption in embedded use cases to growing deployments across a set of additional markets, one of the main questions I am asked relates to the readiness of software optimized for this processor architecture. Over the recent holiday period, I reflected on the significant progress on this front during 2024. The intent of this blog is to tie together a number of the important RISC-V software milestones and provide some hints as to the vector of travel for the year ahead.

Let’s start with the foundational elements of open source software. For many in the RISC-V ecosystem, this means the great work underway in the RISE Project whose stated mission is to accelerate the development of open source software for the RISC-V architecture. 

 More specifically, this group of companies is coordinating and collaborating on the creation of high quality and high performance implementations of RISC-V across a range of areas including:

• Compilers and toolchains
• System libraries
• Kernel and virtualization
• Language runtimes
• Simulators/emulators
• Developer infrastructure

Some of the key milestones during 2024 included:

• Making Java v17, 21, 22, 23, 24 language runtimes available
• Distributing foundational Python packages
• Publishing the RISC-V Optimization Guide
• Adding QEMU support for ACPI for PLIC and NUMA, RISC-V IOMMU, SMBIOS, and the RVA22 Profile Debugging/profiling:
• Upstreamed support of RISC-V vectors for a range of clients
• Linux kernel: Upstreaming of interrupt (AIA) drivers with device tree (DT) and ACPI support

There are more details about the RISE Project’s work in this December webinar, along with some details of RISE’s plans for 2025.

A key theme for 2024 was optimizing software to harness RISC-V vector instructions. From my perspective, one of the best presentations last year that discussed the results of this work was the session by Nathan Egge (Google)) that focused on optimizing the dav1d software decoder for RISC-V.

2025 efforts will focus on supporting the hardware that aligns to the RVA23 Profile that was recently ratified. RVA23 compliant hardware will be seeded out into the developer community from a range of companies, including SiFive. Having a common set of instructions that software can rely on to be present is vital to enable a software ecosystem—arguably multiple different ecosystems for a range of markets including consumer, data center and automotive—to coalesce.

At SiFive, one area of primary focus for software is delivering code that is optimized for our processors. As a part of that, one of the areas we have heavily focused on for the last few years is (not surprisingly!) artificial intelligence (AI). There is clearly a big industry focus on running large language models (LLMs) and RISC-V is well suited for optimally running these workloads. SiFive recently showcased one example of a reference software stack (below) and discussed the performance we had seen from internal tests as part of a webinar. 

In this diagram of an AI system above, blue blocks represent the components that SiFive leverages from and contributes back to open source projects. The yellow blocks represent components provided by third-party vendors or communities, which SiFive leverages. The orange blocks represent the fundamental RISC-V building blocks, primarily owned and maintained by SiFive. A big part of my role here at SiFive has been driving our broad technology portfolio into the data center. As we engaged with hyperscalers, it was clear that companies were designing and maintaining a range of dedicated servers performing functions that include:

• Storage
• Content delivery
• Load balancing
• Web services
• Networking
• Application services

When I talk to customers, many are surprised to hear that, with the exception of the last categories listed above, the software is in place NOW for RISC-V based hardware to run these workloads. Want to see how CEPH runs? You got it. Interested in Memcached? Okay! Particularly passionate about NGINX? Well, you get the picture. Of course, it is fair to say that this work is never done. For all areas, we envision pursuing the approach outlined in the slide below, with an iterative approach to porting and optimizing. This includes optimizing a range of software stacks for the RVA23 Profile. 

In summary, while a lot of software work has been completed, there is a lot of work remaining ahead for the RISC-V community. We will prioritize our efforts based on the stated needs of our customers and continue to work closely with RISE and others to continue the rapid ecosystem growth. We welcome active participation from companies that want to see how SiFive and the RISC-V community at large are addressing their needs, and we would love to hear more about areas that you view are currently underserved. SiFive is eager to collaborate with you on your next project and show you how 2025 is going to be a big year for RISC-V software readiness. To get in touch with the SiFive team, please visit here.