Cache Coherent Verification - New Features in AMBA CHI
May 31, 2021
Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.
AMBA®CHI-E built on top of existing AMBA® CHI-D (Issue D) specification (refer to our blog on AMBA®CHI-D), introduces the support for– a set of new transactions, exclusive access features, transaction optimizations, series of performance throughput improvement features and key Arm architecture features.
Some of the new features include:
To read the full article, click here
Related Semiconductor IP
- PCI Express to AMBA 4 AXI/3 AXI Bridge
- PCIe Controller for USB4 supporting up to PCIe 4.0 with AMBA interface
- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits with AMBA bridge
- PCIe 5.0 (Gen5) Premium Controller with AMBA bridge II
Related Blogs
- Introducing new AMBA 5 CHI protocol enhancements
- Synopsys AMBA CHI C2C System Verification Solutions
- Charting a Productive New Course for AI in Chip Design
- AI Is Driving a New Frontier in Chip Design
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview