Cache Coherent Verification - New Features in AMBA CHI
Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.
AMBA®CHI-E built on top of existing AMBA® CHI-D (Issue D) specification (refer to our blog on AMBA®CHI-D), introduces the support for– a set of new transactions, exclusive access features, transaction optimizations, series of performance throughput improvement features and key Arm architecture features.
Some of the new features include:
To read the full article, click here
Related Semiconductor IP
- Simulation VIP for AMBA CHI
- AMBA 5 CHI Verification IP
- AMBA 5 CHI Verification IP
- AMBA 5 CHI Synthesizable Transactor
- AMBA 5 CHI Assertion IP
Related Blogs
- Synopsys AMBA CHI C2C System Verification Solutions
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring
Latest Blogs
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design