Cache Coherent Verification - New Features in AMBA CHI
May 31, 2021
Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.
AMBA®CHI-E built on top of existing AMBA® CHI-D (Issue D) specification (refer to our blog on AMBA®CHI-D), introduces the support for– a set of new transactions, exclusive access features, transaction optimizations, series of performance throughput improvement features and key Arm architecture features.
Some of the new features include:
To read the full article, click here
Related Semiconductor IP
- AMBA 5 CHI Verification IP
- AMBA 5 CHI Synthesizable Transactor
- AMBA 5 CHI Assertion IP
- AMBA 5 CHI Verification IP
Related Blogs
- Introducing new AMBA 5 CHI protocol enhancements
- Synopsys AMBA CHI C2C System Verification Solutions
- Charting a Productive New Course for AI in Chip Design
- AI Is Driving a New Frontier in Chip Design