AMBA 5 CHI Synthesizable Transactor

Overview

Key Features

• Compliant with the latest ARM AMBA 5 CHI specification (CHI-B).
• Supports CHI Master, Slave, Interconnect.
• Support for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
• Supports all CHI protocol node types:
• Request Nodes (RN-F, RN-D and RN-I)
• Home Nodes (HN-F, HN-I and MN)
• Slave Nodes (SN-F and SN-I)
• Supports Link initialization as per specs.
• Support for skipping link initialization and retrying failed link initialization.
• Configurable credit including dynamic and pre-allocated credit control.
• Cache model support in Master and Interconnect (programmable)
• Support for Speculative read and Snoop filtering.
• Support for all Transaction types and Opcodes.
• Supports Direct Memory Transfer and Direct Cache Transfer.
• Supports Exclusive accesses, Cache Stashing, DVM Operations.
• Supports Deallocating transactions, Poison and Data Check.
• Supports all ARM AMBA 5 CHI data widths.
• Support for Request transactions with/without a Retry and cancelling of transactions.
• Ability to issue multiple outstanding Non-snoopable/Snoopable transactions.
• Programmable Protocol flit delays and different channels delays. Interconnect has the ability to replicate RN/SN inserted delays.
• Supports all write/read responses and snoop responses.
• Fine grain control of below:
• Requester transaction including main memory access
• Completer response to a Requester transaction and Requester acknowledgment/response to Completer's response
• Interconnect generated snoop transaction to Snooped RNs
• Interconnect generated main memory access transactions.
• Snooped RN response to a snoop transaction.
• Supports fine grain control of response per address or per transaction.
• Device and Normal memory types support.
• Support for ordering of transactions/responses and reordering of data packets.
• Support for error injection during Link initialization.
• Ability to inject errors during transfers.
• Supports programmable timeout insertion.
• Supports FIFO memory.
• Rich set of configuration parameters to control CHI functionality.
• Supports on-the-fly protocol and data checking including port level and system level checks.
• Callbacks in Master, Slave and Interconnect for various events.
• AMBA 5 CHI Synthesizable IP comes with complete testsuite to test every feature of ARM AMBA 5 CHI specification.

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the AMBA 5 CHI testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all class, task and functions used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications