Axiomise: Formal, Especially for RISC-V
I recently talked to Ashish Darbari, the CEO of Axiomise. They are based in London, where Ashish ended up having bounced around the world. But more of that later. I also discovered that he would be presenting at CadenceLIVE In Munich the following week, so I planned to attend that presentation and discuss that in this post too.
If you've never heard of Axiomise, let me tell you what they do. They have a four-pronged approach to the market.
To read the full article, click here
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Related Blogs
- Raising RISC-V processor quality with formal verification
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- Improving RISC-V Processor Quality with Verification Standards and Advanced Methodologies
- Synopsys TileLink Interconnect Verification IP for RISC-V SoCs
Latest Blogs
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production