Automating Data Coherency and Performance Testing of High-Speed SoCs with CXL Interfaces

By _Cadence Blog

January 19, 2023

2023 is here, and technology trends around Compute Express Link (CXL) and the next generation of AMBA protocols (CHI-E/F) are getting more traction. The biggest challenge of today is the complexity of handling enormous data flow owning to AI, ML, and deep learning applications. To keep up with the pace, new generation interfaces introduce specialized semantics catering to memory disaggregation, cache consistency, techniques to optimize hardware utilization and efficient transaction flows. Verification challenges for system integrators and verification engineers augmented significantly with the advent of these complex interfaces.

Cadence, a leader in the verification space, pilots much-needed system-level solutions to ease bring-up, testing and debug effort and minimize verification cycles for system integrators. This solution is called ‘System Verification IP,’ which includes System Traffic Libraries, System Testbench Generator, System Verification Scoreboard, and System Performance Analyzer. In this blog, we will talk about the system verification scoreboard (SVD) and system performance analyzer (SPA) taking a real life example of workload submission from CHI interface to CXL nodes through ARM CMN700 interconnect.

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