65nm to 45nm SerDes IP Migration Success Story
May 27, 2011
The problem: To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.
The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).
After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
Related Blogs
- 4nm 112G-ELR SerDes PHY IP
- Cadence Demonstrates 112G-ELR SerDes IP on TSMC's 3nm Process Technology
- When Attempts To Establish IP Empires Died
- Process technology analysis: Navigating analog IP migration with precision
Latest Blogs
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production