65nm to 45nm SerDes IP Migration Success Story
May 27, 2011
The problem: To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.
The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).
After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.
To read the full article, click here
Related Semiconductor IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
Related Blogs
- 4nm 112G-ELR SerDes PHY IP
- Cadence Demonstrates 112G-ELR SerDes IP on TSMC's 3nm Process Technology
- When Attempts To Establish IP Empires Died
- Process technology analysis: Navigating analog IP migration with precision
Latest Blogs
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet
- Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow
- Accelerate Automotive System Design with Cadence AI-Driven DSPs
- What Makes FPGA Architecture Ideal for Ultra-Low-Latency Systems?
- Introducing agileSecure anti-tamper security portfolio