4 Reasons for Bluetooth 5 Adoption in IoT
IoT devices have to be connected but power consumption is usually a real concern. If you think about wearables, like for example fitness wristbands, the time between charges could make or break the product. Even if Wi-Fi looks attractive to connect an IoT device, the system developers have quickly realize that the power consumption associated with Wi-Fi technology was too high, leading to short active time before recharging. Bluetooth 4.0 (aka Low Energy or BTLE) has generated high interest from the developers of emerging IoT applications.
But Bluetooth has been initially defined for short range usage, typically headset and smartphone, with paired device broadcasting approach. According with Bluetooth SIG, the future launch of Bluetooth 5 at the end of 2016, beginning of 2017, will not only suppress these limitations in term of range and broadcasting capability, but also double the speed and by consequence half the power consumption. Let’s review in details these four improvements and their impact on Bluetooth 5 adoption for battery powered connected devices.
To read the full article, click here
Related Semiconductor IP
- Bluetooth 5.3 Dual Mode PHY IP
- Bluetooth 5.4 LE Controller with Link Layer, optional 802.15.4 MAC, early access to Channel Sounding
- Multi-protocol wireless plaform integrating 802.11ax (Wi-Fi 6), Bluetooth 5.4 Dual Mode, 802.15.4 (for Thread, Zigbee and Matter)
- Bluetooth 5.2 / 5.1 / 5.0 / 4.2 LE Host
- Bluetooth 5.3 LE Host
Related Blogs
- 5G Based LEO satellites will Truly Grow IoT Adoption Worldwide
- Is Smart Bluetooth de facto standard for IoT Wearable, Beacons, Fitness and Health ?
- ARM Cordio IP achieves Bluetooth 5 qualification right out of the gate
- Bluetooth 5, 4.2, Bluetooth Classic, and Bluetooth LE...Confused Yet?
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA