Truechip声明首例PCIe 4.0综合验证IP(CVIP)交付客户
Feb 19, 2016 - Truechip Solutions, the verification IP specialist, announced today that it has shipped early adopter versions of its PCIe Gen4 Comprehensive Verification IP (CVIP) to its partners in the early adoption program.
CVIPs are natively developed in SystemVerilog and UVM, and are architected such that a single VIP is able to provide comprehensive, seamless block, SoC and System Level Verification across dynamic simulation, assertion based dynamic and formal verification, as well as support for hardware acceleration and emulation. The CVIP is compatible with all industry leading simulators and hardware platforms.
Nitin Kishore, CEO of Truechip, said in a statement, “PCIe Gen4 hasone of the highest data transfer rate (16 GT/s) which is double to that of PCIe Gen 3! There are also additional power management states for more power saving.PCIe Gen4 also has complete backward support for all its previous versions, which make it more popular in terms of meeting needs of different SOCs. Release of this CVIP, helps in meeting needs of our customers moving to such high speed technology standards”
To try out any of Truechip's high quality CVIPs or experience industry's first 24X5 support, please visit www.truechip.net.
About Truechip
Truechip is a leading provider of Verification IP solutions. Our products enable our customers to lower risks and costs associated with design and verification of their SoC, ASIC or FPGAs.
Truechip is also a member of MIPI Alliance (www.mipi.org) and also provides Verification IPs for MIPI interfaces. MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem and are committed to defining and promoting interface specifications for mobile devices.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Truechip 宣布向客户正式配发PCIe Gen 6 验证 IP
- Analog Bits展示采用TSMC 7nm / 12nm / 16nm / 22nm工艺技术的PCIe Gen2 / Gen3 / Gen4 Reference Clock PHY设计套件
- PLDA®宣布推出Robust Verification Toolset,以提高搭载CXL®、PCIe® 6.0或Gen-Z® Interconnect的下一代SoC的设计精度并缩短生产时间
- Truechip宣布向客户成功提交USB4以及eUSB验证IP