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DES IP

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Compare 10 DES IP from 10 vendors (1 - 10)
  • 3DES Crypto Engine
    • The DES/3DES crypto engine offers a hardware implementation of the Data Encryption Standard (DES) according to Federal Information Processing Standards Publication (FIPS 46-3) of the National Institute of Standards and Technology (NIST).
    Block Diagram -- 3DES Crypto Engine
  • Ultra-Compact Data Encryption Standard (DES/3DES) Core
    • Encrypts and decrypts using the DES / TDEA / Triple DES / 3DES Block Cipher Algorithm
    • High throughput: up to 3 Gbps at 750 MHz in 90 nm LV technology
    • Small size: from 3K ASIC gates for a triple DES core
    • Satisfies FIPS 46-3 from the US National Institute of Standards and Technology (NIST)
    Block Diagram -- Ultra-Compact Data Encryption Standard (DES/3DES) Core
  • Triple DES core
    • Implemented according to the X9.52 standard
    • Implementation based on NIST certified DES core
    • Also available in CBC, CFB and OFB modes.
    • 112 or 168 bits keys supported.
    Block Diagram -- Triple DES core
  • DES/TDES core
    • Standard (1 round per cycle) and Fast (2 rounds per cycle) RTL variants
    • FIPS PUB 46-3 and NIST SP 800-67 compliant Single and Triple DES
    • 64-bit and 192-bit key words
    • ECB, CBC, CFB and OFB modes.
    Block Diagram -- DES/TDES core
  • AHB DES and Triple DES with DMA
    • The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus.
    • The Controller encrypts or decrypts blocks of data based on the DES encryption standard.
    • In order to accommodate a wide variety of system requirements, the Engine can be generated in two modes: LowLatency and LowGateCount. For a TDES system, three DES cores are instantiated.
    Block Diagram -- AHB DES and Triple DES with DMA
  • 3DES ECB/CBC Accelerators
    • The 3DES-IP-16 (EIP-16) is IP for accelerating the AES symmetric cipher algorithm (FIPS-46/81 – SP800-IP-20), supporting single Des and triple DES in ECB, CBC, CFB and OFB modes up to 4 Gbps @ 800MHz.
    • Designed for fast integration, low gate count and full transforms, the 3DES-IP-16 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.
    Block Diagram -- 3DES ECB/CBC Accelerators
  • 3DES
    • Implements Triple DES to latest FIPS PUB 46-3
    • Drop-in module for Spartan-6™, Virtex-6™, Artix-7™, Kintex-7™, Virtex-7™ FPGAs and Zynq™
    • Single clock
    • Supports 192-bit key size (168-bit cipher key with 24 additional parity bits)
    Block Diagram -- 3DES
  • Cryptographic engine using the DES, Triple-DES or AES
    • The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
  • DES Encryption and Decryption Processor
    • Fully compliant 56-Bit key DES implementation
    • Single DES operation
    • Encryption and decryption are performed in 16 clock cycles
    • Suitable for ECB, CBC, CFB and OFB implementations
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